The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such highdensity and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
To increase the number of pad sites available for a die, to reduce the electrical path to the pad sites, and to address other problems, various chip packaging techniques have been developed. One of these techniques is referred to as controlled collapse chip connection or "flip-chip" packaging. With packaging technology, bonding pads of the die include metal (solder) bumps. Electrical connection to the package is made when the die is "flipped" over and soldered to the package. Each bump connects to a corresponding package inner lead. The resulting packages are low profile and have low electrical resistance and a short electrical path. The output terminals of the package, which are sometimes ball-shaped conductive bump contacts, are typically disposed in a rectangular array. These packages are occasionally referred to as "Ball Grid Array" (BGA) packages. Alternatively, the output terminals of the package may be pins and such packages are commonly known as pin grid array (PGA) packages.
Once the die is attached to such a package the back side portion of the die remains exposed. The transistors and other circuitry are generally formed in a very thin epitaxially-grown silicon layer on a single crystal silicon wafer from which the die is singulated. The side of the die including the epitaxial layer containing the transistors, and the other active circuitry is often referred to as the circuit side of the die or front side of the die. The circuit side of the die is positioned very near the package. The circuit side opposes the back side of the die. Between the back side and the circuit side of the die is single crystalline silicon.
The positioning of the circuit side near the package provides many of the advantages of flip chip. However, in some instances orienting the die with the circuit side face down on a substrate is disadvantageous. Due to this orientation of the die, the transistors and circuitry near the circuit side are not directly accessible for testing, modification or other purposes. Therefore, access to the transistors and circuitry near the circuit side is from the back side of the chip.
In order to access desired circuitry within the device, it is helpful to "view" the circuitry to determine its location. Viewing the circuitry within the chip via the back side using optical or scanning electron microscopy is blocked by the bulk silicon. Infrared (IR) microscopy, however, is capable of imaging the circuit through the silicon because the silicon is relatively transparent in these wavelengths of the radiation. To acquire these images, because of the absorption losses of IR radiation in silicon, it is generally required to thin the die to less than 100 microns. For example, on a die that is 725 microns thick, at least 625 microns of silicon is typically removed before IR microscopy can be used. Thinning the die for failure analysis of a flip chip bonded IC is usually accomplished by first thinning the die across the whole die surface, often referred to as global thinning. Mechanical polishing, such as chemical-mechanical polishing (CMP), is one method for global thinning.
Once an area is identified using IR microscopy as an area of interest and it is determined that access is needed to a particular area of the circuit, local thinning techniques are often used to thin an area smaller than the die size. One method of local thinning, referred to as laser microchemical etching, is typically accomplished by focussing a laser beam on the back side of the silicon surface to cause local melting of silicon in the presence of chlorine gas. The molten silicon reacts very rapidly with chlorine and forms silicon tetrachloride gas, which leaves the molten (reaction) zone. This is a silicon removal process used in connection with the 9850 SiliconEtcher.TM. tool by Revise, Inc. (Burlington, Mass). This laser process is suitable for both local and global thinning by scanning the laser over a part or whole surface of the die.
Sometimes it is helpful for failure analysis, or for design debug, to make electrical contact and probe certain nodes in the circuit that is on the circuit side or front side of the die, or to reconfigure the conductors in an integrated circuit. This access is generally done by milling through the die to access the node, or milling to the node and subsequently depositing a metal to electrically access the node. These access holes need to have high aspect ratios. Milling through silicon with fairly high aspect ratio trenches is slow and almost impractical for ratios greater than 5:1.times.Depth:Width. For these reasons, it is necessary to have a method and apparatus which will provide for controlled thinning of flip chip bonded IC devices to within a few microns of the active circuitry. In particular, it is important to have the ability to determine the endpoint of the removal process with sufficient accuracy to avoid milling off the node to which access is being sought, which could often jeopardize further device analysis. The endpoint may be a preliminary or final endpoint of the removal process.
Therefore, the introduction of flip chips and other semiconductor technologies that use back side analysis would benefit from a method and apparatus for determining the thickness of silicon between a portion of the active circuitry near the circuit side of the die and the back side of the die. This is beneficial for eliminating any guesswork as to the thickness of the silicon while the back side of the die is being removed. If this guesswork is eliminated, failure analysis and debugging of the circuitry associated with a particular integrated circuit is facilitated. Furthermore, when the position of the circuitry is known or can be determined from the back side removal of the silicon, getting to the circuitry can be accomplished in less time.